Such a semiconductor device is known from U.S. Pat. No. 5,607,871. In the known semiconductor device, the non-volatile memory cell comprises a source and a drain, and an access gate which is electrically isolated from a gate structure comprising a control gate. The gate structure is electrically insulated from the semiconductor body by a gate dielectric which is provided with a floating gate acting as a charge-storage region wherein data in the form of electric charge can be stored. The access gate has a substantially flat surface portion extending substantially parallel to the surface of the semiconductor body. The access gate is provided by a patterned polysilicon layer which overlaps the gate structure as well as an adjacent gate structure and stretches out to substantially beyond the outermost side walls of the gate structures. In between the gate structures, the patterned polysilicon layer is disposed above the drain, which is locally provided in the semiconductor body. The source is provided in the semiconductor body, while being aligned to the patterned polysilicon layer.
A disadvantage of the known semiconductor device is that, owing to the large topography at the location of the gate structures and, hence, of a polysilicon layer applied on top of these gate structures, photolithographic patterning of the polysilicon layer is difficult. When a photoresist layer formed on top of the polysilicon layer is exposed to light so as to form a resist pattern, the exposed light is reflected in oblique directions on the surface of the polysilicon layer. As a consequence, the resist pattern is deformed, resulting in a poor dimensional accuracy of the patterned polysilicon layer. As the patterned polysilicon layer is disposed above the drain, other disadvantages of the known semiconductor device are that the source and the drain cannot be formed in a single step and that cross-talk takes place between the patterned polysilicon layer and the drain during operation of the memory cell.
The above-described non-volatile memory cell comprises an access transistor and a floating gate transistor, which floating gate transistor comprises a floating gate whereon data in the form of electric charge can be stored. As is well known to those skilled in the art, a so-called charge trapping transistor can be used instead of the above-mentioned floating gate transistor. Such a charge trapping transistor comprises a control gate which is electrically insulated from the semiconductor body by a gate dielectric, which gate dielectric comprises a distribution of mutually separated trapping centers wherein electric charge can be stored. In such a charge trapping transistor, electric charge cannot only be provided throughout the length of the channel but also only on the source side of the channel or only on the drain side of the channel. Since these different conditions can be distinguished in the reading process, it is possible to store two bits per memory cell.
Whether a floating gate is used for charge storage, as is the case in the known semiconductor device, or a gate dielectric comprising mutually separated trapping centers makes no difference with regard to the above-mentioned disadvantages. These disadvantages also occur in a semiconductor device with a charge trapping transistor.